// Copyright (C) 1953-2022 NUDT
// Verilog module name - opensync_mac
// Version: V4.0.0.20221115
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         opensync enable mac
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps

module opensync_mac
(
        i_clk,
        i_rst_n,
        
        iv_hcp_mid        ,
        i_local_cnt_rst   ,                
        i_tsn_or_tte      ,	

        iv_command_osm_0         ,   
        i_command_wr_osm_0       ,
        ov_command_ack_osm_0     ,
        o_command_ack_wr_osm_0   ,
        
        iv_command_osm_1         , 
        i_command_wr_osm_1       ,
        ov_command_ack_osm_1     ,
        o_command_ack_wr_osm_1   ,
                           
        iv_command_osm_2         ,
        i_command_wr_osm_2       ,
        ov_command_ack_osm_2     ,
        o_command_ack_wr_osm_2   ,
                          
        iv_command_osm_3         , 
        i_command_wr_osm_3       ,
        ov_command_ack_osm_3     ,
        o_command_ack_wr_osm_3   ,
                            
        iv_command_osm_4         ,  
        i_command_wr_osm_4       ,
        ov_command_ack_osm_4     ,
        o_command_ack_wr_osm_4   ,
                          
        iv_command_osm_5         ,
        i_command_wr_osm_5       ,
        ov_command_ack_osm_5     ,
        o_command_ack_wr_osm_5   ,
                          
        iv_command_osm_6         , 
        i_command_wr_osm_6       ,
        ov_command_ack_osm_6     ,
        o_command_ack_wr_osm_6   ,
                       
        iv_command_osm_7         , 
        i_command_wr_osm_7       ,
        ov_command_ack_osm_7     ,
        o_command_ack_wr_osm_7   ,
        //p0
        i_gmii_clk_p0,
        i_gmii_rst_n_p0,        
        iv_gmii_rxd_p0  ,
        i_gmii_rx_dv_p0 ,
        i_gmii_rx_er_p0 ,        
        ov_gmii_txd_p0  ,
        o_gmii_tx_en_p0 ,
        o_gmii_tx_er_p0 ,    
        
        iv_data_p0,
        i_data_wr_p0,
        o_data_ready_p0,        
            
        ov_data_p0,
        o_data_wr_p0, 
        //p1 					
        i_gmii_clk_p1,
        i_gmii_rst_n_p1,        
        iv_gmii_rxd_p1  ,
        i_gmii_rx_dv_p1 ,
        i_gmii_rx_er_p1 ,        
        ov_gmii_txd_p1  ,
        o_gmii_tx_en_p1 ,
        o_gmii_tx_er_p1 ,    
        
        iv_data_p1,
        i_data_wr_p1,
        o_data_ready_p1,          
            
        ov_data_p1,
        o_data_wr_p1,
        //p2
        i_gmii_clk_p2,
        i_gmii_rst_n_p2,        
        iv_gmii_rxd_p2  ,
        i_gmii_rx_dv_p2 ,
        i_gmii_rx_er_p2 ,        
        ov_gmii_txd_p2  ,
        o_gmii_tx_en_p2 ,
        o_gmii_tx_er_p2 ,    
        
        iv_data_p2,
        i_data_wr_p2, 
        o_data_ready_p2,          
            
        ov_data_p2,
        o_data_wr_p2, 
        //p3	
        i_gmii_clk_p3,
        i_gmii_rst_n_p3,        
        iv_gmii_rxd_p3  ,
        i_gmii_rx_dv_p3 ,
        i_gmii_rx_er_p3 ,        
        ov_gmii_txd_p3  ,
        o_gmii_tx_en_p3 ,
        o_gmii_tx_er_p3 ,    
        
        iv_data_p3,
        i_data_wr_p3,
        o_data_ready_p3,        
            
        ov_data_p3,
        o_data_wr_p3,
        //p4
        i_gmii_clk_p4,
        i_gmii_rst_n_p4,        
        iv_gmii_rxd_p4  ,
        i_gmii_rx_dv_p4 ,
        i_gmii_rx_er_p4 ,        
        ov_gmii_txd_p4  ,
        o_gmii_tx_en_p4 ,
        o_gmii_tx_er_p4 ,    
        
        iv_data_p4,
        i_data_wr_p4,
        o_data_ready_p4,        
            
        ov_data_p4,
        o_data_wr_p4,  
        //p5
        i_gmii_clk_p5,
        i_gmii_rst_n_p5,        
        iv_gmii_rxd_p5  ,
        i_gmii_rx_dv_p5 ,
        i_gmii_rx_er_p5 ,        
        ov_gmii_txd_p5  ,
        o_gmii_tx_en_p5 ,
        o_gmii_tx_er_p5 ,    
        
        iv_data_p5,
        i_data_wr_p5,
        o_data_ready_p5,        
            
        ov_data_p5,
        o_data_wr_p5,   
        //p6
        i_gmii_clk_p6,
        i_gmii_rst_n_p6,        
        iv_gmii_rxd_p6  ,
        i_gmii_rx_dv_p6 ,
        i_gmii_rx_er_p6 ,        
        ov_gmii_txd_p6  ,
        o_gmii_tx_en_p6 ,
        o_gmii_tx_er_p6 ,    
        
        iv_data_p6,
        i_data_wr_p6,
        o_data_ready_p6,        
            
        ov_data_p6,
        o_data_wr_p6,
        //p7
        i_gmii_clk_p7,
        i_gmii_rst_n_p7,        
        iv_gmii_rxd_p7  ,
        i_gmii_rx_dv_p7 ,
        i_gmii_rx_er_p7 ,        
        ov_gmii_txd_p7  ,
        o_gmii_tx_en_p7 ,
        o_gmii_tx_er_p7 ,    
        
        iv_data_p7,
        i_data_wr_p7,
        o_data_ready_p7,        
            
        ov_data_p7,
        o_data_wr_p7,

        o_osm_req_rx_pulse_p0    ,
        o_osm_resp_rx_pulse_p0   ,
        o_osm_req_tx_pulse_p0    ,
        o_osm_resp_tx_pulse_p0   ,
        
        o_osm_req_rx_pulse_p1    ,
        o_osm_resp_rx_pulse_p1   ,
        o_osm_req_tx_pulse_p1    ,
        o_osm_resp_tx_pulse_p1   ,
        
        o_osm_req_rx_pulse_p2    ,
        o_osm_resp_rx_pulse_p2   ,
        o_osm_req_tx_pulse_p2    ,
        o_osm_resp_tx_pulse_p2   ,
        
        o_osm_req_rx_pulse_p3    ,
        o_osm_resp_rx_pulse_p3   ,
        o_osm_req_tx_pulse_p3    ,
        o_osm_resp_tx_pulse_p3   ,
        
        o_osm_req_rx_pulse_p4    ,
        o_osm_resp_rx_pulse_p4   ,
        o_osm_req_tx_pulse_p4    ,
        o_osm_resp_tx_pulse_p4   ,
        
        o_osm_req_rx_pulse_p5    ,
        o_osm_resp_rx_pulse_p5   ,
        o_osm_req_tx_pulse_p5    ,
        o_osm_resp_tx_pulse_p5   ,
        
        o_osm_req_rx_pulse_p6    ,
        o_osm_resp_rx_pulse_p6   ,
        o_osm_req_tx_pulse_p6    ,
        o_osm_resp_tx_pulse_p6   ,
        
        o_osm_req_rx_pulse_p7    ,
        o_osm_resp_rx_pulse_p7   ,
        o_osm_req_tx_pulse_p7    ,
        o_osm_resp_tx_pulse_p7      
);

// I/O
input                   i_clk         ;                   //125Mhz
input                   i_rst_n       ;

input       [11:0]      iv_hcp_mid     ;
input                   i_tsn_or_tte   ;  
input                   i_local_cnt_rst;

input       [63:0]      iv_command_osm_0         ;  
input                   i_command_wr_osm_0       ;
output      [63:0]      ov_command_ack_osm_0     ;
output                  o_command_ack_wr_osm_0   ;
          
input       [63:0]      iv_command_osm_1         ;
input                   i_command_wr_osm_1       ;
output      [63:0]      ov_command_ack_osm_1     ;
output                  o_command_ack_wr_osm_1   ;
                   
input       [63:0]      iv_command_osm_2         ;  
input                   i_command_wr_osm_2       ;
output      [63:0]      ov_command_ack_osm_2     ;
output                  o_command_ack_wr_osm_2   ;
                  
input       [63:0]      iv_command_osm_3         ; 
input                   i_command_wr_osm_3       ;
output      [63:0]      ov_command_ack_osm_3     ;
output                  o_command_ack_wr_osm_3   ;
                    
input       [63:0]      iv_command_osm_4         ;  
input                   i_command_wr_osm_4       ;
output      [63:0]      ov_command_ack_osm_4     ;
output                  o_command_ack_wr_osm_4   ;
                  
input       [63:0]      iv_command_osm_5         ; 
input                   i_command_wr_osm_5       ;
output      [63:0]      ov_command_ack_osm_5     ;
output                  o_command_ack_wr_osm_5   ;
                  
input       [63:0]      iv_command_osm_6         ;  
input                   i_command_wr_osm_6       ;
output      [63:0]      ov_command_ack_osm_6     ;
output                  o_command_ack_wr_osm_6   ;
               
input       [63:0]      iv_command_osm_7         ;
input                   i_command_wr_osm_7       ;
output      [63:0]      ov_command_ack_osm_7     ;
output                  o_command_ack_wr_osm_7   ;
/////////////////////p0////////////////////
// clk & rst
input                   i_gmii_clk_p0    ;
input                   i_gmii_rst_n_p0  ;  		
//input data from gmii
input        [7:0]      iv_gmii_rxd_p0   ;
input                   i_gmii_rx_dv_p0  ;
input                   i_gmii_rx_er_p0  ;
//output data to swc
output       [8:0]      ov_data_p0;
output                  o_data_wr_p0;
//input data from swc
input        [8:0]      iv_data_p0;
input                   i_data_wr_p0;
output                  o_data_ready_p0;
//output data to gmii
output       [7:0]      ov_gmii_txd_p0;
output                  o_gmii_tx_en_p0;
output                  o_gmii_tx_er_p0;
/////////////////////p1////////////////////
// clk & rst
input                   i_gmii_clk_p1    ;
input                   i_gmii_rst_n_p1  ; 
//input data from gmii
input        [7:0]      iv_gmii_rxd_p1   ;
input                   i_gmii_rx_dv_p1  ;
input                   i_gmii_rx_er_p1  ;
//output data to swc
(*MARK_DEBUG="true"*)output       [8:0]      ov_data_p1;
(*MARK_DEBUG="true"*)output                  o_data_wr_p1;
//input data from swc
(*MARK_DEBUG="true"*)input        [8:0]      iv_data_p1;
(*MARK_DEBUG="true"*)input                   i_data_wr_p1;
                     output                  o_data_ready_p1;
//output data to gmii
output       [7:0]      ov_gmii_txd_p1;
output                  o_gmii_tx_en_p1;
output                  o_gmii_tx_er_p1;
/////////////////////p2////////////////////
// clk & rst
input                   i_gmii_clk_p2    ;
input                   i_gmii_rst_n_p2  ;
//input data from gmii
input        [7:0]      iv_gmii_rxd_p2   ;
input                   i_gmii_rx_dv_p2  ;
input                   i_gmii_rx_er_p2  ;
//output data to swc
(*MARK_DEBUG="true"*)output       [8:0]      ov_data_p2;
(*MARK_DEBUG="true"*)output                  o_data_wr_p2;
//input data from swc
(*MARK_DEBUG="true"*)input        [8:0]      iv_data_p2;
(*MARK_DEBUG="true"*)input                   i_data_wr_p2;
                     output                  o_data_ready_p2;
//output data to gmii
output       [7:0]      ov_gmii_txd_p2;
output                  o_gmii_tx_en_p2;
output                  o_gmii_tx_er_p2;
/////////////////////p3////////////////////
// clk & rst
input                   i_gmii_clk_p3    ;
input                   i_gmii_rst_n_p3  ;   
//input data from gmii
input        [7:0]      iv_gmii_rxd_p3   ;
input                   i_gmii_rx_dv_p3  ;
input                   i_gmii_rx_er_p3  ;
//output data to swc
(*MARK_DEBUG="true"*)output       [8:0]      ov_data_p3;
(*MARK_DEBUG="true"*)output                  o_data_wr_p3;
//input data from swc
(*MARK_DEBUG="true"*)input        [8:0]      iv_data_p3;
(*MARK_DEBUG="true"*)input                   i_data_wr_p3;
                     output                  o_data_ready_p3;
//output data to gmii
output       [7:0]      ov_gmii_txd_p3;
output                  o_gmii_tx_en_p3;
output                  o_gmii_tx_er_p3;
/////////////////////p4////////////////////
// clk & rst
input                   i_gmii_clk_p4    ;
input                   i_gmii_rst_n_p4  ;  
//input data from gmii
input        [7:0]      iv_gmii_rxd_p4   ;
input                   i_gmii_rx_dv_p4  ;
input                   i_gmii_rx_er_p4  ;
//output data to swc
output       [8:0]      ov_data_p4;
output                  o_data_wr_p4;
//input data from swc
input        [8:0]      iv_data_p4;
input                   i_data_wr_p4;
output                  o_data_ready_p4;
//output data to gmii
output       [7:0]      ov_gmii_txd_p4;
output                  o_gmii_tx_en_p4;
output                  o_gmii_tx_er_p4;
/////////////////////p5////////////////////
// clk & rst
input                   i_gmii_clk_p5    ;
input                   i_gmii_rst_n_p5  ;    
//input data from gmii
input        [7:0]      iv_gmii_rxd_p5   ;
input                   i_gmii_rx_dv_p5  ;
input                   i_gmii_rx_er_p5  ;
//output data to swc
output       [8:0]      ov_data_p5;
output                  o_data_wr_p5;
//input data from swc
input        [8:0]      iv_data_p5;
input                   i_data_wr_p5;
output                  o_data_ready_p5;
//output data to gmii
output       [7:0]      ov_gmii_txd_p5;
output                  o_gmii_tx_en_p5;
output                  o_gmii_tx_er_p5;
/////////////////////p6////////////////////
// clk & rst
input                   i_gmii_clk_p6    ;
input                   i_gmii_rst_n_p6  ;  
//input data from gmii
input        [7:0]      iv_gmii_rxd_p6   ;
input                   i_gmii_rx_dv_p6  ;
input                   i_gmii_rx_er_p6  ;
//output data to swc
output       [8:0]      ov_data_p6;
output                  o_data_wr_p6;
//input data from swc
input        [8:0]      iv_data_p6;
input                   i_data_wr_p6;
output                  o_data_ready_p6;
//output data to gmii
output       [7:0]      ov_gmii_txd_p6;
output                  o_gmii_tx_en_p6;
output                  o_gmii_tx_er_p6;
/////////////////////p7////////////////////
// clk & rst
input                   i_gmii_clk_p7    ;
input                   i_gmii_rst_n_p7  ;  
//input data from gmii
input        [7:0]      iv_gmii_rxd_p7   ;
input                   i_gmii_rx_dv_p7  ;
input                   i_gmii_rx_er_p7  ;
//output data to swc
output       [8:0]      ov_data_p7;
output                  o_data_wr_p7;
//input data from swc
input        [8:0]      iv_data_p7;
input                   i_data_wr_p7;
output                  o_data_ready_p7;
//output data to gmii
output       [7:0]      ov_gmii_txd_p7;
output                  o_gmii_tx_en_p7;
output                  o_gmii_tx_er_p7; 

output                  o_osm_req_rx_pulse_p0    ;
output                  o_osm_resp_rx_pulse_p0   ;
output                  o_osm_req_tx_pulse_p0    ;
output                  o_osm_resp_tx_pulse_p0   ;

output                  o_osm_req_rx_pulse_p1    ;
output                  o_osm_resp_rx_pulse_p1   ;
output                  o_osm_req_tx_pulse_p1    ;
output                  o_osm_resp_tx_pulse_p1   ;

output                  o_osm_req_rx_pulse_p2    ;
output                  o_osm_resp_rx_pulse_p2   ;
output                  o_osm_req_tx_pulse_p2    ;
output                  o_osm_resp_tx_pulse_p2   ;

output                  o_osm_req_rx_pulse_p3    ;
output                  o_osm_resp_rx_pulse_p3   ;
output                  o_osm_req_tx_pulse_p3    ;
output                  o_osm_resp_tx_pulse_p3   ;

output                  o_osm_req_rx_pulse_p4    ;
output                  o_osm_resp_rx_pulse_p4   ;
output                  o_osm_req_tx_pulse_p4    ;
output                  o_osm_resp_tx_pulse_p4   ;

output                  o_osm_req_rx_pulse_p5    ;
output                  o_osm_resp_rx_pulse_p5   ;
output                  o_osm_req_tx_pulse_p5    ;
output                  o_osm_resp_tx_pulse_p5   ;

output                  o_osm_req_rx_pulse_p6    ;
output                  o_osm_resp_rx_pulse_p6   ;
output                  o_osm_req_tx_pulse_p6    ;
output                  o_osm_resp_tx_pulse_p6   ;

output                  o_osm_req_rx_pulse_p7    ;
output                  o_osm_resp_rx_pulse_p7   ;
output                  o_osm_req_tx_pulse_p7    ;
output                  o_osm_resp_tx_pulse_p7   ;
/*
output                  o_osm_req_rx_pulse_p8    ;
output                  o_osm_resp_rx_pulse_p8   ;
output                  o_osm_req_tx_pulse_p8    ;
output                  o_osm_resp_tx_pulse_p8   ;

output                  o_osm_req_rx_pulse_p9    ;
output                  o_osm_resp_rx_pulse_p9   ;
output                  o_osm_req_tx_pulse_p9    ;
output                  o_osm_resp_tx_pulse_p9   ;

output                  o_osm_req_rx_pulse_p10    ;
output                  o_osm_resp_rx_pulse_p10   ;
output                  o_osm_req_tx_pulse_p10    ;
output                  o_osm_resp_tx_pulse_p10   ;

output                  o_osm_req_rx_pulse_p11    ;
output                  o_osm_resp_rx_pulse_p11   ;
output                  o_osm_req_tx_pulse_p11    ;
output                  o_osm_resp_tx_pulse_p11   ;

output                  o_osm_req_rx_pulse_p12    ;
output                  o_osm_resp_rx_pulse_p12   ;
output                  o_osm_req_tx_pulse_p12    ;
output                  o_osm_resp_tx_pulse_p12   ;

output                  o_osm_req_rx_pulse_p13    ;
output                  o_osm_resp_rx_pulse_p13   ;
output                  o_osm_req_tx_pulse_p13    ;
output                  o_osm_resp_tx_pulse_p13   ;

output                  o_osm_req_rx_pulse_p14    ;
output                  o_osm_resp_rx_pulse_p14   ;
output                  o_osm_req_tx_pulse_p14    ;
output                  o_osm_resp_tx_pulse_p14   ;

output                  o_osm_req_rx_pulse_p15    ;
output                  o_osm_resp_rx_pulse_p15   ;
output                  o_osm_req_tx_pulse_p15    ;
output                  o_osm_resp_tx_pulse_p15   ;

output                  o_osm_req_rx_pulse_p16    ;
output                  o_osm_resp_rx_pulse_p16   ;
output                  o_osm_req_tx_pulse_p16    ;
output                  o_osm_resp_tx_pulse_p16   ;

output                  o_osm_req_rx_pulse_p17    ;
output                  o_osm_resp_rx_pulse_p17   ;
output                  o_osm_req_tx_pulse_p17    ;
output                  o_osm_resp_tx_pulse_p17   ;

output                  o_osm_req_rx_pulse_p18    ;
output                  o_osm_resp_rx_pulse_p18   ;
output                  o_osm_req_tx_pulse_p18    ;
output                  o_osm_resp_tx_pulse_p18   ;

output                  o_osm_req_rx_pulse_p19    ;
output                  o_osm_resp_rx_pulse_p19   ;
output                  o_osm_req_tx_pulse_p19    ;
output                  o_osm_resp_tx_pulse_p19   ;

output                  o_osm_req_rx_pulse_p20    ;
output                  o_osm_resp_rx_pulse_p20   ;
output                  o_osm_req_tx_pulse_p20    ;
output                  o_osm_resp_tx_pulse_p20   ;

output                  o_osm_req_rx_pulse_p21    ;
output                  o_osm_resp_rx_pulse_p21   ;
output                  o_osm_req_tx_pulse_p21    ;
output                  o_osm_resp_tx_pulse_p21   ;

output                  o_osm_req_rx_pulse_p22    ;
output                  o_osm_resp_rx_pulse_p22   ;
output                  o_osm_req_tx_pulse_p22    ;
output                  o_osm_resp_tx_pulse_p22   ;

output                  o_osm_req_rx_pulse_p23    ;
output                  o_osm_resp_rx_pulse_p23   ;
output                  o_osm_req_tx_pulse_p23    ;
output                  o_osm_resp_tx_pulse_p23   ;

output                  o_osm_req_rx_pulse_p24    ;
output                  o_osm_resp_rx_pulse_p24   ;
output                  o_osm_req_tx_pulse_p24    ;
output                  o_osm_resp_tx_pulse_p24   ;

output                  o_osm_req_rx_pulse_p25    ;
output                  o_osm_resp_rx_pulse_p25   ;
output                  o_osm_req_tx_pulse_p25    ;
output                  o_osm_resp_tx_pulse_p25   ;

output                  o_osm_req_rx_pulse_p26    ;
output                  o_osm_resp_rx_pulse_p26   ;
output                  o_osm_req_tx_pulse_p26    ;
output                  o_osm_resp_tx_pulse_p26   ;

output                  o_osm_req_rx_pulse_p27    ;
output                  o_osm_resp_rx_pulse_p27   ;
output                  o_osm_req_tx_pulse_p27    ;
output                  o_osm_resp_tx_pulse_p27   ;

output                  o_osm_req_rx_pulse_p28    ;
output                  o_osm_resp_rx_pulse_p28   ;
output                  o_osm_req_tx_pulse_p28    ;
output                  o_osm_resp_tx_pulse_p28   ;

output                  o_osm_req_rx_pulse_p29    ;
output                  o_osm_resp_rx_pulse_p29   ;
output                  o_osm_req_tx_pulse_p29    ;
output                  o_osm_resp_tx_pulse_p29   ;

output                  o_osm_req_rx_pulse_p30    ;
output                  o_osm_resp_rx_pulse_p30   ;
output                  o_osm_req_tx_pulse_p30    ;
output                  o_osm_resp_tx_pulse_p30   ;

output                  o_osm_req_rx_pulse_p31    ;
output                  o_osm_resp_rx_pulse_p31   ;
output                  o_osm_req_tx_pulse_p31    ;
output                  o_osm_resp_tx_pulse_p31   ;
*/
opensync_1gmac #(.osm_id(8'd0),.local_module_id(12'd1)) opensync_1gmac_p0
(                    
.i_gmii_clk        (i_gmii_clk_p0              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p0            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_command        (iv_command_osm_0             ),
.i_command_wr      (i_command_wr_osm_0           ),
.ov_command_ack    (ov_command_ack_osm_0         ),     
.o_command_ack_wr  (o_command_ack_wr_osm_0       ),					 

.iv_hcp_mid        (iv_hcp_mid                ),                                               
.i_local_cnt_rst   (i_local_cnt_rst           ),       
                   
.i_port_type       (1'b0                       ),
.i_tsn_or_tte      (i_tsn_or_tte               ),
              
.i_gmii_rx_dv      (i_gmii_rx_dv_p0            ),
.i_gmii_rx_er      (i_gmii_rx_er_p0            ),
.iv_gmii_rxd       (iv_gmii_rxd_p0             ),
.o_gmii_tx_en      (o_gmii_tx_en_p0            ),
.o_gmii_tx_er      (o_gmii_tx_er_p0            ),
.ov_gmii_txd       (ov_gmii_txd_p0             ),
                                               
.i_data_wr         (i_data_wr_p0               ),
.iv_data           (iv_data_p0                 ),
.o_data_ready      (o_data_ready_p0            ),
.o_data_wr         (o_data_wr_p0               ),
.ov_data           (ov_data_p0                 ),

.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p0 ),
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p0),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p0 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p0)

);

opensync_1gmac #(.osm_id(8'd1),.local_module_id(12'd2))opensync_1gmac_p1
(                    
.i_gmii_clk        (i_gmii_clk_p1              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p1            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_command        (iv_command_osm_1          ),
.i_command_wr      (i_command_wr_osm_1        ),
.ov_command_ack    (ov_command_ack_osm_1      ),     
.o_command_ack_wr  (o_command_ack_wr_osm_1    ),

.iv_hcp_mid        (iv_hcp_mid                ),                                                
.i_local_cnt_rst   (i_local_cnt_rst           ),       
                   
.i_port_type       (1'b0                       ),
.i_tsn_or_tte      (i_tsn_or_tte               ),
              
.i_gmii_rx_dv      (i_gmii_rx_dv_p1            ),
.i_gmii_rx_er      (i_gmii_rx_er_p1            ),
.iv_gmii_rxd       (iv_gmii_rxd_p1             ),
.o_gmii_tx_en      (o_gmii_tx_en_p1            ),
.o_gmii_tx_er      (o_gmii_tx_er_p1            ),
.ov_gmii_txd       (ov_gmii_txd_p1             ),
                                               
.i_data_wr         (i_data_wr_p1               ),
.iv_data           (iv_data_p1                 ),
.o_data_ready      (o_data_ready_p1            ),
.o_data_wr         (o_data_wr_p1               ),
.ov_data           (ov_data_p1                 ),

.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p1 ),
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p1),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p1 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p1)

);

opensync_1gmac #(.osm_id(8'd2),.local_module_id(12'd3))opensync_1gmac_p2
(                    
.i_gmii_clk        (i_gmii_clk_p2              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p2            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_command        (iv_command_osm_2           ),
.i_command_wr      (i_command_wr_osm_2         ),
.ov_command_ack    (ov_command_ack_osm_2       ),     
.o_command_ack_wr  (o_command_ack_wr_osm_2     ),

.iv_hcp_mid        (iv_hcp_mid                ),                                                
.i_local_cnt_rst   (i_local_cnt_rst           ),       
                   
.i_port_type       (1'b0                       ),
.i_tsn_or_tte      (i_tsn_or_tte               ),
              
.i_gmii_rx_dv      (i_gmii_rx_dv_p2            ),
.i_gmii_rx_er      (i_gmii_rx_er_p2            ),
.iv_gmii_rxd       (iv_gmii_rxd_p2             ),
.o_gmii_tx_en      (o_gmii_tx_en_p2            ),
.o_gmii_tx_er      (o_gmii_tx_er_p2            ),
.ov_gmii_txd       (ov_gmii_txd_p2             ),
                                               
.i_data_wr         (i_data_wr_p2               ),
.iv_data           (iv_data_p2                 ),
.o_data_ready      (o_data_ready_p2            ),
.o_data_wr         (o_data_wr_p2               ),
.ov_data           (ov_data_p2                 ),

.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p2 ),
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p2),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p2 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p2)

);

opensync_1gmac #(.osm_id(8'd3),.local_module_id(12'd4))opensync_1gmac_p3
(                    
.i_gmii_clk        (i_gmii_clk_p3              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p3            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_command        (iv_command_osm_3            ),
.i_command_wr      (i_command_wr_osm_3          ),
.ov_command_ack    (ov_command_ack_osm_3        ),     
.o_command_ack_wr  (o_command_ack_wr_osm_3      ),

.iv_hcp_mid        (iv_hcp_mid                ),                                                 
.i_local_cnt_rst   (i_local_cnt_rst           ),       
                   
.i_port_type       (1'b0                       ),
.i_tsn_or_tte      (i_tsn_or_tte               ),
              
.i_gmii_rx_dv      (i_gmii_rx_dv_p3            ),
.i_gmii_rx_er      (i_gmii_rx_er_p3            ),
.iv_gmii_rxd       (iv_gmii_rxd_p3             ),
.o_gmii_tx_en      (o_gmii_tx_en_p3            ),
.o_gmii_tx_er      (o_gmii_tx_er_p3            ),
.ov_gmii_txd       (ov_gmii_txd_p3             ),
                                               
.i_data_wr         (i_data_wr_p3               ),
.iv_data           (iv_data_p3                 ),
.o_data_ready      (o_data_ready_p3            ),
.o_data_wr         (o_data_wr_p3               ),
.ov_data           (ov_data_p3                 ),

.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p3 ),
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p3),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p3 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p3)

);

opensync_1gmac #(.osm_id(8'd4),.local_module_id(12'd5))opensync_1gmac_p4
(                    
.i_gmii_clk        (i_gmii_clk_p4              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p4            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_command        (iv_command_osm_4           ),
.i_command_wr      (i_command_wr_osm_4         ),
.ov_command_ack    (ov_command_ack_osm_4       ),     
.o_command_ack_wr  (o_command_ack_wr_osm_4     ),

.iv_hcp_mid        (iv_hcp_mid                ),                                                 
.i_local_cnt_rst   (i_local_cnt_rst           ),       
                   
.i_port_type       (1'b0                       ),
.i_tsn_or_tte      (i_tsn_or_tte               ),
              
.i_gmii_rx_dv      (i_gmii_rx_dv_p4            ),
.i_gmii_rx_er      (i_gmii_rx_er_p4            ),
.iv_gmii_rxd       (iv_gmii_rxd_p4             ),
.o_gmii_tx_en      (o_gmii_tx_en_p4            ),
.o_gmii_tx_er      (o_gmii_tx_er_p4            ),
.ov_gmii_txd       (ov_gmii_txd_p4             ),
                                               
.i_data_wr         (i_data_wr_p4               ),
.iv_data           (iv_data_p4                 ),
.o_data_ready      (o_data_ready_p4            ),
.o_data_wr         (o_data_wr_p4               ),
.ov_data           (ov_data_p4                 ),

.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p4 ),
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p4),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p4 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p4)

);

opensync_1gmac #(.osm_id(8'd5),.local_module_id(12'd6))opensync_1gmac_p5
(                    
.i_gmii_clk        (i_gmii_clk_p5              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p5            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_command        (iv_command_osm_5          ),
.i_command_wr      (i_command_wr_osm_5        ),
.ov_command_ack    (ov_command_ack_osm_5      ),     
.o_command_ack_wr  (o_command_ack_wr_osm_5    ),

.iv_hcp_mid        (iv_hcp_mid                ),                                                 
.i_local_cnt_rst   (i_local_cnt_rst           ),       
                   
.i_port_type       (1'b0                       ),
.i_tsn_or_tte      (i_tsn_or_tte               ),
              
.i_gmii_rx_dv      (i_gmii_rx_dv_p5            ),
.i_gmii_rx_er      (i_gmii_rx_er_p5            ),
.iv_gmii_rxd       (iv_gmii_rxd_p5             ),
.o_gmii_tx_en      (o_gmii_tx_en_p5            ),
.o_gmii_tx_er      (o_gmii_tx_er_p5            ),
.ov_gmii_txd       (ov_gmii_txd_p5             ),
                                               
.i_data_wr         (i_data_wr_p5               ),
.iv_data           (iv_data_p5                 ),
.o_data_ready      (o_data_ready_p5            ),
.o_data_wr         (o_data_wr_p5               ),
.ov_data           (ov_data_p5                 ),

.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p5 ),
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p5),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p5 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p5)

);

opensync_1gmac #(.osm_id(8'd6),.local_module_id(12'd7))opensync_1gmac_p6
(                    
.i_gmii_clk        (i_gmii_clk_p6              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p6            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_command        (iv_command_osm_6            ),
.i_command_wr      (i_command_wr_osm_6          ),
.ov_command_ack    (ov_command_ack_osm_6        ),     
.o_command_ack_wr  (o_command_ack_wr_osm_6      ),

.iv_hcp_mid        (iv_hcp_mid                ),                                                 
.i_local_cnt_rst   (i_local_cnt_rst           ),       
                   
.i_port_type       (1'b0                       ),
.i_tsn_or_tte      (i_tsn_or_tte               ),
              
.i_gmii_rx_dv      (i_gmii_rx_dv_p6            ),
.i_gmii_rx_er      (i_gmii_rx_er_p6            ),
.iv_gmii_rxd       (iv_gmii_rxd_p6             ),
.o_gmii_tx_en      (o_gmii_tx_en_p6            ),
.o_gmii_tx_er      (o_gmii_tx_er_p6            ),
.ov_gmii_txd       (ov_gmii_txd_p6             ),
                                               
.i_data_wr         (i_data_wr_p6               ),
.iv_data           (iv_data_p6                 ),
.o_data_ready      (o_data_ready_p6            ),
.o_data_wr         (o_data_wr_p6               ),
.ov_data           (ov_data_p6                 ),

.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p6 ),
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p6),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p6 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p6)

);

opensync_1gmac #(.osm_id(8'd7),.local_module_id(12'd8))opensync_1gmac_p7
(                    
.i_gmii_clk        (i_gmii_clk_p7              ),                   
.i_gmii_rst_n      (i_gmii_rst_n_p7            ),                                               
.i_clk             (i_clk                      ),
.i_rst_n           (i_rst_n                    ),

.iv_command        (iv_command_osm_7          ),
.i_command_wr      (i_command_wr_osm_7        ),
.ov_command_ack    (ov_command_ack_osm_7      ),     
.o_command_ack_wr  (o_command_ack_wr_osm_7    ),

.iv_hcp_mid        (iv_hcp_mid                ),                                                 
.i_local_cnt_rst   (i_local_cnt_rst           ),       
                   
.i_port_type       (1'b0                       ),
.i_tsn_or_tte      (i_tsn_or_tte               ),
              
.i_gmii_rx_dv      (i_gmii_rx_dv_p7            ),
.i_gmii_rx_er      (i_gmii_rx_er_p7            ),
.iv_gmii_rxd       (iv_gmii_rxd_p7             ),
.o_gmii_tx_en      (o_gmii_tx_en_p7            ),
.o_gmii_tx_er      (o_gmii_tx_er_p7            ),
.ov_gmii_txd       (ov_gmii_txd_p7             ),
                                               
.i_data_wr         (i_data_wr_p7               ),
.iv_data           (iv_data_p7                 ),
.o_data_ready      (o_data_ready_p7            ),
.o_data_wr         (o_data_wr_p7               ),
.ov_data           (ov_data_p7                 ),

.o_osm_req_rx_pulse (o_osm_req_rx_pulse_p7 ),
.o_osm_resp_rx_pulse(o_osm_resp_rx_pulse_p7),
.o_osm_req_tx_pulse (o_osm_req_tx_pulse_p7 ),
.o_osm_resp_tx_pulse(o_osm_resp_tx_pulse_p7)

);

endmodule 